This invention relates to floating gate devices, and more particularly to programmable floating gate devices useful as a programmable link to function as a fusible link.
In memory circuits, it has been found that yield can be improved by using redundancy techniques. Accordingly, techniques for implementing redundant rows and columns have been developed. These include links selectively opened by a laser, polysilicon fuses selectively opened by high current, and floating gate transistors selectively programmed by a high voltage. Disadvantages of the laser technique include the large capital investment for the laser equipment and alignment problems due to the relatively large number of alignments which must be made to implement a redundant row or column. Disadvantages of polysilicon fuses include the high current requirement which is very difficult in MOS technology and requires an opening in the passivation layer which consequently requires a further processing step or die coating at the stage the die is assembled into a package. Disadvantages of the floating gate technique include requiring a high voltage for programming and consequently requiring special circuit design to avoid having the high voltage adversely effect the decoder circuit which also receives the high voltage under existing techniques. U.S. patent application Ser. No. 321,855, Kuo, entitled "Electrically Erasable Programmable Read Only Memory Cell," filed Nov. 16, 1981, now U.S. Pat. No. 4,479,203, and assigned to the assignee hereof, describes a technique for erasing a programmed floating gate transistor by extending the floating gate and the control gate of a control transistor to an area which is remote from the programmed transistor to facilitate erasing. The considerations for programming a floating gate transistor, however, are different from those for erasing.